The present invention relates to a method of manufacturing semiconductor devices particularly suitable for manufacturing mask ROMs.
A conventional method of manufacturing mask ROMs is described, for example, in the technique disclosed in Japanese Patent Laid-Open Publication No. 1-158734. This technique will be explained with reference to FIG. 6 showing cross sections of a mask ROM at each manufacturing step. As shown in FIG. 6(a), a silicon oxide film 602 having a thickness of 200 angstroms is formed on the surface of a semiconductor substrate 601 by means of thermal oxidization under an atmosphere of oxygen containing hydrochloric acid at 900.degree. C. Polysilicon is deposited on the silicon oxide film 602 to a film thickness of 4000 angstroms by means of a low pressure chemical vapor deposition (LPCVD) method. Phosphors are thermally diffused into the formed polysilicon film 603 under a phosphoryl chloride (POCl.sub.3) atmosphere. A silicon oxide film 604 is formed on the surface of the device by means of a CVD method. Resist is coated on the surface of the silicon oxide film 604 to form a resist film 605 patterned so as to cover every second gate electrode area.
Using the resist film 605 as a mask, the silicon oxide film 604 is etched by a reactive ion etching method to form a gate oxide film 604a such as shown in FIG. 6(b). The resist film 605 is removed, and resist is again coated and patterned to form a resist film 606 at the area where the gate oxide film 604 is not present.
Next, reactive ion etching is performed with a high selective etching ratio providing an etching speed of the polysilicon film 603 sufficiently faster than that of the gate oxide film 604. As a result, the polysilicon film 603 is etched at the narrow area where the resist film 606 and silicon oxide film 604a are not present. By removing the resist film 606, gate electrodes 603a with a small clearance space therebetween are formed such as shown in FIG. 6(c).
Another conventional method has been used heretofore. This method can reduce a variation of clearances between gate electrodes. This method will be explained with reference to FIG. 7. Similar to the above-described method, a silicon oxide film 702 and polysilicon film 703 are formed on a semiconductor substrate 701 in this order as shown in FIG. 7(a). Phosphors are thermally diffused in the polysilicon film 703. A silicon oxide film 704 is formed on the polysilicon film 703 to a thickness of 4000 angstroms by means of a CVD method. Resist is coated to form a resist film 705 patterned so as to cover every second gate electrode area.
Using the resist film 705 as a mask, the silicon oxide film 704 is etched by a reactive ion etching method to obtain a silicon oxide film 704a shown in FIG. 7(b). Polysilicon is deposited to a thickness of 1000 angstroms by means of an LPCVD method, and etched by an isotropic, reactive ion etching method to form side walls 706 on the sides of the silicon oxide film 704.
As shown in FIG. 7(c), a silicon oxide film 707 is deposited on the whole surface of the device as shown in FIG. 7(c). The thickness of the silicon oxide film 707 is about 4000 angstroms which is about one half of the distance between patterns of the silicon oxide film 704a. After coating resist and flattening the surface of the device, it is etched back by means of a reactive ion etching method to obtain a silicon oxide film 704b whose thickness is thinner than the side walls 706 as shown in FIG. 7(d).
The polysilicon side walls 706 and polysilicon film 703 are etched by a reactive ion etching method to leave a polysilicon film 703a and silicon oxide film 704c on the gate oxide film 702. In this manner, gate electrodes are formed in a self-alignment manner with a constant clearance between gate electrodes.
Examples of devices having gate electrodes formed by the above-described conventional methods are shown in FIGS. 8 and 9. FIG. 8 shows a large scale integrated NOR type mask ROM of a virtual ground array type, and FIG. 9 shows a large scale integrated NAND type mask ROM. In the ROM shown in FIG. 8, buried n.sup.+ diffusion regions 801, 802, 803, . . . are formed on the surface of a semiconductor substrate at a constant pitch, and gate electrodes 811, 812, 813, . . . are formed on the surface of the device perpendicular to the diffusion regions. Such an array layout is disclosed in Sharp Technical Review, pp. 71 to 75, Vol. 40, 1988. Impurity ions are implanted into areas 821 and 822 to write data. In the ROM shown in FIG. 9, element forming areas 901 and 902 surrounded by an element isolation area 900 are formed on the surface of a semiconductor substrate. Contact areas 921 and 922 connected to wiring layers are formed within the respective element forming areas 901 and 902. Gate electrodes 911, 912, 913, . . . are formed perpendicular to the element forming areas 901 and 902, and impurity ions are implanted into areas 931 and 932. For such ROMs having gate electrodes formed at a narrow pitch, it is necessary to inject data writing impurity ions into a desired area at a high precision.
Impurity ions are implanted in the following manner. As shown in FIG. 10(a), a silicon oxide film 1002 is formed on the surface of a semiconductor substrate 1001, and polysilicon gate electrodes 1003a, 1003b, . . . are disposed. Resist is coated and patterned to remove it only at the areas where impurity ions are implanted into the channel regions under the gate electrodes 1003a, 1003b, . . . . In this case, the end face of the resist film 1004 is aligned with the center between the gate electrodes 1003a and 1003b. A silicon oxide film formed on the polysilicon gate electrodes has been etched out by using ammonium fluoride solution.
Boron ions (B.sup.+) are implanted at a dose of 1.times.10.sup.14 cm.sup.-2 and at an acceleration voltage of about 160 keV in order to raise the threshold voltage of an N-channel transistor constituting a memory cell of a NOR type ROM. The width of the gate electrode is set to 0.6 .mu.m, and a clearance is set to 0.1 .mu.m, for example. If the end face of the resist film 1004 is precisely aligned with the center between gate electrodes such as shown in FIG. 10(a), then impurity ions are implanted into a region 1011 near the substrate surface under the gate electrode 1003a, and into a deeper region 1012 at the gap between the gate electrode 1003a and the resist film 1004. The region 1012 is so deep from the surface of the semiconductor substrate 1001 that the threshold voltage at the channel region is not influenced. Ions are precisely implanted into the region 1011 corresponding to the width of the subject gate electrode 1003a near the substrate surface, and are not implanted near to the substrate surface of the adjacent gate electrode 1003b.
However, if the position of the resist film 1004 is misaligned such as shown in FIG. 10(b), the following problem occurs. Assuming that the end face of the resist film 1004 is misaligned by 0.2 .mu.m which is three times (3.sigma.) as large as the standard deviation, impurity ions are implanted not only into the channel region 1011 of the subject gate electrode 1003a, but also into the channel region 1013 of the adjacent gate electrode 1003b.
Thermal treatment after implantation of impurity ions causes the ions to diffuse by about 0.1 .mu.m in the lateral direction. Therefore, as shown in FIG. 10(c), impurity ions are diffused by 0.25 .mu.m into the channel region of the adjacent gate electrode 1003b. As a result, in the NOR type ROM shown in FIG. 8, the channel width of a cell transistor is shortened and the memory cell current is reduced greatly by about 0.6 [(0.6-0.25)/0.6].
In the case of the NAND type ROM shown in FIG. 9, the channel length is shortened, resulting in a possible punch-through or leakage current at the element isolation area 900.
As described above, with the conventional manufacturing methods, misalignment of a resist film causes impurity ions to be implanted into the area under an adjacent gate electrode, resulting in a reduced cell current and punch-through.